/* * 74181 is straight from Fairchild's 74F181 data sheet. */ module sn74181 (s3, s2, s1, s0, m, a3, a2, a1, a0, b3, b2, b1, b0, f3, f2, f1, f0, ci, co, g, p, abeq); input m; input s3, s2, s1, s0; input a3, a2, a1, a0; input b3, b2, b1, b0; output f3, f2, f1, f0; input ci; output co, p, g, abeq; wire p0 = !(a0 | (s0 & b0) | (s1 & !b0)); wire p1 = !(a1 | (s0 & b1) | (s1 & !b1)); wire p2 = !(a2 | (s0 & b2) | (s1 & !b2)); wire p3 = !(a3 | (s0 & b3) | (s1 & !b3)); wire g0 = !((!b0 & s2 & a0) | (a0 & b0 & s3)); wire g1 = !((!b1 & s2 & a1) | (a1 & b1 & s3)); wire g2 = !((!b2 & s2 & a2) | (a2 & b2 & s3)); wire g3 = !((!b3 & s2 & a3) | (a3 & b3 & s3)); wire u0 = !(ci & !m); wire u1 = !m & p0; wire u2 = !m & ci & g0; wire u3 = !m & p1; wire u4 = !m & p0 & g1; wire u5 = !m & ci & g0 & g1; wire u6 = !m & p2; wire u7 = !m & p1 & g2; wire u8 = !m & p0 & g1 & g2; wire u9 = !m & ci & g0 & g1 & g2; wire u10 = !(g0 & g1 & g2 & g3); wire u11 = !(ci & g0 & g1 & g2 & g3); wire u12 = p0 & g1 & g2 & g3; wire u13 = p1 & g2 & g3; wire u14 = p2 & g3; wire u15 = p3; wire u16 = !(u12 | u13 | u14 | u15); // propagation delays are from the data sheet and are the max. // delays. assign #13 f0 = u0 ^ p0 ^ g0; assign #13 f1 = !(u1 | u2) ^ p1 ^ g1; assign #13 f2 = !(u3 | u4 | u5) ^ p2 ^ g2; assign #13 f3 = !(u6 | u7 | u8 | u9) ^ p3 ^ g3; assign #15 co = !u11 | !u16; assign #11 p = u10; assign #10 g = u16; assign #29 abeq = (f0 & f1 & f2 & f3) ? 1'b0 : 1'bZ; // OC endmodule