A very simple 16-bit RISC ISA

This is my take at a simple 16-bit ISA.

Encoding                 Mnemonic               

0000 ddd sss ttt ???     AND Rd, Rs, Rt         Rd ← Rs & Rt
0001 ddd sss iii iii     AND Rd, Rs, #imm       Rd ← Rs & sex(imm)

0010 ddd sss ttt ???     ADD Rd, Rs, Rt         Rd ← Rs + Rt
0011 ddd sss iii iii     ADD Rd, Rs, #imm       Rd ← Rs + sex(imm)

0100 ddd sss ttt ???     XOR Rd, Rs, Rt         Rd ← Rs ^ Rt
0101 ddd sss iii iii     XOR Rd, Rs, #imm       Rd ← Rs ^ sex(imm)

0110 ddd sss ttt ???     LDR Rd, [Rs + Rt]      Rd ← mem[Rs + Rt]
0111 ddd sss iii iii     LDR Rd, [Rs + #imm]    Rd ← mem[Rs + imm]

1000 ddd sss ttt ???     STR Rd, [Rs + Rt]      mem[Rs + Rt] ← Rd
1001 ddd sss iii iii     STR Rd, [Rs + #imm]    mem[Rs + imm] ← Rd

101o ooo ooo ooo ooo     JMP offset             R7 ← R7 + sex(imm)
110o ooo ooo ooo ooo     JIN offset             R7 ← R7 + sex(imm), if N flag set
111o ooo ooo ooo ooo     JIZ offset             R7 ← R7 + sex(imm), if Z flag set

All instructions instructions but the jump insturctions affect the Z and N flags. The Z is set, if after an instruction Rd is zero. The N flag is set, if after an instruction Rd is negative.

Memory is word addressed.

The program counter is in the R7 register.

sex(x) means to sign extend the value x.

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Gilbert Baumann, 2021-11-17