A Serial Shifter

Shift instruction

The shift instruction has opcode #xA and carries the shift count and kind in the address part. It chould do left and right shifts, and rotations.

+------+------+----------------------------------+
| 1010 | 0000 | 0000 0000 0000 0000 0 a r d nnnn |
+------------------------------------------------+

16-n = shift count

d   0 = do left
    1 = do right

r   0 = do shift
    1 = do rotation

a   0 = do logic shift
    1 = do arithmetic shift

Pseudo Instructions

We provide pseudo instructions for the conventional operations and names. The argument n must be constant and is not an address to be dereferenced.

The machine could only shift/rotate by 1 to 16 bits in either direction. The assembler supports the full argument range for n as a signed word. For rotation arguments larger than 16, we rotate the other way around.

For shifts larger than 16, we rotate left and then mask with and, so that you get two instructions. For asr we would need to have two asrs for arguments larger than 16.

shl  n
Pseudo Instruction

A ← A << n, CF and VF undefined

Shift the accumulator left by n bits. When n is negative shift the accumulator right by -n bits. If |n| ≥ 32 then A is set to zero.

shr  n
Pseudo Instruction

A ← A >> n, CF and VF undefined

Shift the accumulator right by n bits. When n is negative shift the accumulator left by -n bits. If |n| ≥ 32 then A is set to zero.

asr  n
Pseudo Instruction

Arithmetically shifts the accumulator right. The leftmost bit is copied while shifting. Thus the accumulator keeps its sign and shifting by n is dividing the signed accumulator by 2n.

When n is negative this is equivalent to shr.

rol  n
Pseudo Instruction

Rotate the accumulator left by n bits. If n is negative rotate right.

ror  n
Pseudo Instruction

Rotate the accumulator right by n bits. If n is negative rotate left.

Implementation

Instead of a barrel shifter we use a serial shifter made from the universal 74F299 shift register. It can do left and right shifts as well as parallel loads.

When shifting is due, the shift register is loaded with the accumulator and a 4-bit counter 74161 is loaded with the shift count (16-n really). With each clock cycle this counter is incremented until it reaches #xF at which time shifting is stopped.

The 74F299 has two select lines S0 and S1 which govern what the register should do:

 S1  S0      Action
------------------------------
 0   0       hold, do nothing
 0   1       shift right
 1   0       shift left
 1   1       parallel load

We directly use S[1:0] as the state of a little state machine. The implementation is straight forward with two 1/2 '74s and one '153.

*** schematic here ***

The initial state is 00 and only when in the right clock phase just after the accumulator has been latched and a shift instruction is present, we move to the loading state 11.