Each instruction is a 32-bit word. It has three parts: a 4-bit opcode, a 1-bit addressing mode and a 27 bit address part.
32 28 27 0
+----+-----+----------------------+
| op | imm | addresss |
+----+-----+----------------------+
The opcodes are:
add m - A <- A + [m], CF set if overflow, ZF set if zeroadc m - A <- A + [m] + CF, CF set if overflow, ZF set if zerosub m - A <- A - [m], CF set if underflow, ZF set if zerosbb m - A <- A - [m] - CF, CF set if underflow, ZF set if zeroior m - A <- A ior [m]xor m - A <- A xor [m]and m - A <- A and [m]ror m - A <- A rotated by [m] bits rightjmp m - jump to [m]jz m - jump to [m], if ZF setjnz m - jump to [m], if ZF clearjc m - jump to [m], if CF setjnc m - jump to [m], if CF clearsto m - [m] <- Alod m - A <- [m]