parameter TECH_F = 'd 0; parameter TECH_ACT = 'd 1; parameter TECH_AC = 'd 2; module sn7400 (a, b, y); // nand input a, b; output y; assign #6 y = ~(a & b); // 'F endmodule module sn7402 (a, b, y); // nor parameter tech = TECH_F; parameter TPD = (tech == TECH_F ? 6.5 : tech == TECH_ACT ? 11.1 : (1/0)); // parameter TPD = 11.1; // 'ACT input a, b; output y; assign #(TPD) y = ~(a | b); endmodule module sn7404 (a, y); parameter tech = TECH_F; parameter TPD = (tech == TECH_F ? 6.0 : tech == TECH_AC ? 7.5 : tech == TECH_ACT ? 9.0 : (1e9)); input a; output y; assign #(TPD) y = ~a; // 'F endmodule module sn7408 (a, b, y); // and input a, b; output y; // assign #10 y = a & b; assign #7.5 y = a & b; endmodule module sn7420 (a, b, c, d, y); // 4-input nand input a, b, c, d; output y; assign #10 y = ~(a & b & c & d); // ### endmodule module sn7430 (a, b, c, d, e, f, g, h, // 8-input positive-NAND gate y); input a, b, c, d, e, f, g, h; output y; // 'F timing assign #5.5 y = !(a & b & c & d & e & f & g & h); endmodule module sn7432 (a, b, y); // or input a, b; output y; // 'F: 6.6ns // 'HCT: 30ns assign #6.6 y = a | b; // 'F // assign #23 y = a | b; // 'HC endmodule module sn7436 (a, b, y); // nor input a, b; output y; assign #10 y = ~(a | b); endmodule module sn7486 (a, b, y); // xor input a, b; output y; assign #10 y = a ^ b; endmodule module sn7474 (d, cp, sd, rd, q, nq); // dual d-type flip-flop input d, cp, sd, rd; reg s; output q; output nq; // set takes priority always @(rd) if (!rd) s = 0; always @(sd) if (!sd) s = 1; always @(posedge cp) begin if (sd && rd) s = d; end // assign #50 q = s; // 'hc // assign #50 nq = !s; // 'hc assign #10 q = s; // 'f assign #10 nq = !s; // 'f endmodule module sn74138 (a2, a1, a0, e2, e1, e0, y0, y1, y2, y3, y4, y5, y6, y7); input a2, a1, a0; input e2, e1, e0; output y7, y6, y5, y4, y3, y2, y1, y0; wire [7:0] y; // 'F: 9.5ns assign #10 y7 = ({e2, e1, e0, a2, a1, a0} == 6'b100111) ? 0 : 1; assign #10 y6 = ({e2, e1, e0, a2, a1, a0} == 6'b100110) ? 0 : 1; assign #10 y5 = ({e2, e1, e0, a2, a1, a0} == 6'b100101) ? 0 : 1; assign #10 y4 = ({e2, e1, e0, a2, a1, a0} == 6'b100100) ? 0 : 1; assign #10 y3 = ({e2, e1, e0, a2, a1, a0} == 6'b100011) ? 0 : 1; assign #10 y2 = ({e2, e1, e0, a2, a1, a0} == 6'b100010) ? 0 : 1; assign #10 y1 = ({e2, e1, e0, a2, a1, a0} == 6'b100001) ? 0 : 1; assign #10 y0 = ({e2, e1, e0, a2, a1, a0} == 6'b100000) ? 0 : 1; endmodule module sn74139 (a1, a0, e, y3, y2, y1, y0); input a1, a0; input e; output y3, y2, y1, y0; assign #10 {y3, y2, y1, y0} = (e ? 4'b1111 : (a1 ? (a0 ? 4'b0111 : 4'b1011) : (a0 ? 4'b1101 : 4'b1110))); endmodule // dual 4:1 mux, enable module sn74153 (\1d0 ,\1d1 ,\1d2 ,\1d3 , \2d0 ,\2d1 ,\2d2 ,\2d3 , \1y , \2y , s0, s1, \/1e , \/2e ); input \1d0 ,\1d1 ,\1d2 ,\1d3 ; input \2d0 ,\2d1 ,\2d2 ,\2d3 ; output \1y , \2y ; input s0, s1, oe, \/1e , \/2e ; // 'ACT: 18ns assign #12 \1y = \/1e ? 1'b0 : ((s1 == 1'b0) ? ((s0 == 1'b0) ? \1d0 : \1d1 ) : ((s0 == 1'b0) ? \1d2 : \1d3 )); assign #12 \2y = \/2e ? 1'b0 : ((s1 == 1'b0) ? ((s0 == 1'b0) ? \2d0 : \2d1 ) : ((s0 == 1'b0) ? \2d2 : \2d3 )); endmodule // dual 4:1 mux, 3-state module sn74253 (\1d0 ,\1d1 ,\1d2 ,\1d3 , \2d0 ,\2d1 ,\2d2 ,\2d3 , \1y , \2y , s0, s1, n1oe, n2oe); input \1d0 ,\1d1 ,\1d2 ,\1d3 ; input \2d0 ,\2d1 ,\2d2 ,\2d3 ; output \1y , \2y ; input s0, s1, oe, n1oe, n2oe; assign #10 \1y = n1oe ? 1'bZ : ((s1 == 1'b0) ? ((s0 == 1'b0) ? \1d0 : \1d1 ) : ((s0 == 1'b0) ? \1d2 : \1d3 )); assign #10 \2y = n2oe ? 1'bZ : ((s1 == 1'b0) ? ((s0 == 1'b0) ? \2d0 : \2d1 ) : ((s0 == 1'b0) ? \2d2 : \2d3 )); endmodule // quad 2:1 mux, 3-state // (157 is /e = H => Y = L module sn74257 (\1i0 ,\2i0 ,\3i0 ,\4i0 , \1i1 ,\2i1 ,\3i1 ,\4i1 , \1y , \2y ,\3y ,\4y , s, oe); input \1i0 ,\2i0 ,\3i0 ,\4i0 ; input \1i1 ,\2i1 ,\3i1 ,\4i1 ; output \1y , \2y ,\3y ,\4y ; input s, oe; assign #15 \1y = oe ? 1'bZ : ((s == 1'b0) ? \1i0 : \1i1 ); assign #15 \2y = oe ? 1'bZ : ((s == 1'b0) ? \2i0 : \2i1 ); assign #15 \3y = oe ? 1'bZ : ((s == 1'b0) ? \3i0 : \3i1 ); assign #15 \4y = oe ? 1'bZ : ((s == 1'b0) ? \4i0 : \4i1 ); endmodule module sn74157 (\1i0 ,\2i0 ,\3i0 ,\4i0 , \1i1 ,\2i1 ,\3i1 ,\4i1 , \1y , \2y ,\3y ,\4y , s, e); input \1i0 ,\2i0 ,\3i0 ,\4i0 ; input \1i1 ,\2i1 ,\3i1 ,\4i1 ; output \1y , \2y ,\3y ,\4y ; input s, e; reg s_d, e_d; always @(s) #(11-7) s_d = s; always @(e) #(11-7) e_d = e; // 'F is 11ns (S->Q), but 7ns (I->Y) assign #7 \1y = e_d ? 1'b0 : ((s_d == 1'b0) ? \1i0 : \1i1 ); assign #7 \2y = e_d ? 1'b0 : ((s_d == 1'b0) ? \2i0 : \2i1 ); assign #7 \3y = e_d ? 1'b0 : ((s_d == 1'b0) ? \3i0 : \3i1 ); assign #7 \4y = e_d ? 1'b0 : ((s_d == 1'b0) ? \4i0 : \4i1 ); endmodule module sn74161 (clk, nmr, pe, d0, d1, d2, d3, q0, q1, q2, q3, cep, cet, tc); input clk, nmr, pe, cep, cet; output tc; input d0, d1, d2, d3; output q0, q1, q2, q3; reg [3:0] tmp; always @(nmr) begin if (!nmr) tmp = 4'b0000; end always @(posedge clk) begin if (nmr) begin if (!pe) tmp = {d3, d2, d1, d0}; else if (cep && cet) tmp = tmp + 1'b1; end end assign #10 {q3, q2, q1, q0} = tmp; assign #10 tc = (tmp == 4'b1111) && cet; endmodule // // 74174 - hex d-type flip flop with clear // module sn74174 (d0, d1, d2, d3, d4, d5, q0, q1, q2, q3, q4, q5, \/mr , clk); input d0, d1, d2, d3, d4, d5; input \/mr , clk; output q0, q1, q2, q3, q4, q5; reg [5:0] q; // Asynchronous master reset always @(\/mr ) if (!\/mr ) q = 6'b000000; always @(posedge clk) begin if (\/mr ) q = { d5, d4, d3, d2, d1, d0 }; end assign #11 { q5, q4, q3, q2, q1, q0 } = q; // 'F: on CP endmodule // '175 Quad d-type flip-flop, clear, additional inverted outputs. module sn74175(d0, d1, d2, d3, q0, q1, q2, q3, nq0, nq1, nq2, nq3, clk, clr); input d0, d1, d2, d3; output q0, q1, q2, q3; output nq0, nq1, nq2, nq3; input clk; input clr; reg [3:0] q; // Asynchronous master reset always @(clr) begin if (!clr) q = 4'b0000; end // Clock always @(posedge clk) if (clr) q = { d3, d2, d1, d0}; assign #10 {q3, q2, q1, q0} = q; assign #10 {nq3, nq2, nq1, nq0} = {!q[3], !q[2], !q[1], !q[0]}; endmodule // 8:1 mux, 3-state module sn74251 (d7, d6, d5, d4, d3, d2, d1, d0, s2, s1, s0, oe, y, w); input d7, d6, d5, d4, d3, d2, d1, d0; input s2, s1, s0; input oe; output y, w; // 51ns: 'hc // 9.5ns to W and 12ns to Y ('F151) assign #12 y = oe ? 1'bZ : ((s2 == 1'b1) ? ((s1 == 1'b1) ? ((s0 == 1'b1) ? d7 : d6) : ((s0 == 1'b1) ? d5 : d4)) : ((s1 == 1'b1) ? ((s0 == 1'b1) ? d3 : d2) : ((s0 == 1'b1) ? d1 : d0))); assign #9.5 w = oe ? 1'bZ : !((s2 == 1'b1) ? ((s1 == 1'b1) ? ((s0 == 1'b1) ? d7 : d6) : ((s0 == 1'b1) ? d5 : d4)) : ((s1 == 1'b1) ? ((s0 == 1'b1) ? d3 : d2) : ((s0 == 1'b1) ? d1 : d0))); endmodule // sn74251 // 8:1 mux, enable module sn74151 (d7, d6, d5, d4, d3, d2, d1, d0, s2, s1, s0, e, y, w); input d7, d6, d5, d4, d3, d2, d1, d0; input s2, s1, s0; input e; output y, w; // 46ns 'HC // 11ns 'F assign #11 y = e ? 1'b0 : ((s2 == 1'b1) ? ((s1 == 1'b1) ? ((s0 == 1'b1) ? d7 : d6) : ((s0 == 1'b1) ? d5 : d4)) : ((s1 == 1'b1) ? ((s0 == 1'b1) ? d3 : d2) : ((s0 == 1'b1) ? d1 : d0))); assign #11 w = e ? 1'b1 : !((s2 == 1'b1) ? ((s1 == 1'b1) ? ((s0 == 1'b1) ? d7 : d6) : ((s0 == 1'b1) ? d5 : d4)) : ((s1 == 1'b1) ? ((s0 == 1'b1) ? d3 : d2) : ((s0 == 1'b1) ? d1 : d0))); endmodule // 5-input positive-NOR gate module sn74260 (a, b, c, d, e, y); input a, b, c, d, e; output y; // 'F timing assign #6.6 y = !(a | b | c | d | e); endmodule module sn74283 (a3, a2, a1, a0, b3, b2, b1, b0, c0, s3, s2, s1, s0, c4); input a3, a2, a1, a0; input b3, b2, b1, b0; input c0; output s3, s2, s1, s0; output c4; wire [3:0] a = {a3, a2, a1, a0}; wire [3:0] b = {b3, b2, b1, b0}; wire [4:0] sum = a + b + c0; assign #10 {s3, s2, s1, s0} = sum; assign #10 c4 = sum[4]; endmodule // Universal shift register module sn74299(s0, s1, dsr, dsl, cp, mr, q0, q7, oe1, oe2, io7, io6, io5, io4, io3, io2, io1, io0); input s0, s1; input dsr, dsl, cp, mr; output q0, q7; input oe1, oe2; inout io7, io6, io5, io4, io3, io2, io1, io0; reg [7:0] Q; // Asynchronous master reset always @(mr) begin if (!mr) Q = 8'b00000000; end // Clock always @(posedge cp) begin if (mr) begin case ({s1, s0}) 2'b00: ; // hold 2'b01: Q = (Q << 1) | dsr; // shift "right" 2'b10: Q = (Q >> 1) | (dsl << 7); // shift "left" 2'b11: Q = {io7, io6, io5, io4, io3, io2, io1, io0}; // load endcase end end // output // 'F = 10ns assign #10 q0 = Q[0]; assign #10 q7 = Q[7]; assign #10 {io7, io6, io5, io4, io3, io2, io1, io0} = (({oe2, oe1} == 2'b00) && !({s1, s0} == 2'b11)) ? Q : 8'bZZZZZZZZ; endmodule module sn74541 (g1, g2, a7, a6, a5, a4, a3, a2, a1, a0, y7, y6, y5, y4, y3, y2, y1, y0); input g1, g2; input a7, a6, a5, a4, a3, a2, a1, a0; output y7, y6, y5, y4, y3, y2, y1, y0; // Data to output: 6n // Output enable time: 9.5ns // Output disable time: 6.5ns assign #10 {y7, y6, y5, y4, y3, y2, y1, y0} = ((!g1 && !g2) ? {a7, a6, a5, a4, a3, a2, a1, a0} : 8'bZZZZZZZZ); endmodule module sn74574 (clk, oe, d7, d6, d5, d4, d3, d2, d1, d0, q7, q6, q5, q4, q3, q2, q1, q0); parameter tech = TECH_F; // The CY74FCT574CT // ^^ // can do in 5.2 on CP, and 5.5 on OE parameter TPD = (tech == TECH_F ? 8.5 : tech == TECH_ACT ? 12.0 : 1e9); parameter TOE = (tech == TECH_F ? 10.0 : tech == TECH_ACT ? 12.0 : 1e9); input clk, oe; input d7, d6, d5, d4, d3, d2, d1, d0; output q7, q6, q5, q4, q3, q2, q1, q0; reg [0:7] r; // ### why reverse? wire oe_d; assign #(TOE-TPD) oe_d = oe; // clear the register initially, this is not technically correct, // as the initial value is pretty random. //initial r = 2; // $random; initial begin r = $random; r = $random; // $display("Value of r is %h",r); end always @(posedge clk) // Check for the value being sane. A real flip flop cannot latch // an 'X'. r = {d7 === 1'b0 ? 1'b0 : 1'b1, d6 === 1'b0 ? 1'b0 : 1'b1, d5 === 1'b0 ? 1'b0 : 1'b1, d4 === 1'b0 ? 1'b0 : 1'b1, d3 === 1'b0 ? 1'b0 : 1'b1, d2 === 1'b0 ? 1'b0 : 1'b1, d1 === 1'b0 ? 1'b0 : 1'b1, d0 === 1'b0 ? 1'b0 : 1'b1}; assign #(TPD) {q7, q6, q5, q4, q3, q2, q1, q0} = oe_d ? 8'bZZZZZZZZ : r; endmodule module sn74273 (clk, mr, d7, d6, d5, d4, d3, d2, d1, d0, q7, q6, q5, q4, q3, q2, q1, q0); input clk, mr; input d7, d6, d5, d4, d3, d2, d1, d0; output q7, q6, q5, q4, q3, q2, q1, q0; reg [0:7] r; initial r = $random; // Asynchronous master reset always @(mr) if (!mr) r = 8'b00000000; always @(posedge clk && mr) r = {d7, d6, d5, d4, d3, d2, d1, d0}; assign #10 {q7, q6, q5, q4, q3, q2, q1, q0} = r; endmodule // 4x4 register file module sn74670 (d1, d2, d3, d4, wa, wb, ra, rb, gw, gr, q1, q2, q3, q4); input d1, d2, d3, d4; input wa, wb; input ra, rb; input gw, gr; output q1, q2, q3, q4; reg [0:3] q [0:3]; // device works as a latch always @(gw or d1 or d2 or d3 or d4 or wa or wb) if (!gw) begin q[{wa, wb}] = {d1, d2, d3, d4}; end assign #10 {q1, q2, q3, q4} = gr ? 4'bZZZZ : q[{ra, rb}]; endmodule // 8-bit identity comparator -- obsolete somehow, use '521 instead module sn74688 (p7, p6, p5, p4, p3, p2, p1, p0, q7, q6, q5, q4, q3, q2, q1, q0, g, p_q); input p7, p6, p5, p4, p3, p2, p1, p0; input q7, q6, q5, q4, q3, q2, q1, q0; input g; output p_q; assign #30 // 'hc p_q = !(!g && {p7, p6, p5, p4, p3, p2, p1, p0} == {q7, q6, q5, q4, q3, q2, q1, q0}); endmodule // sn74688 // 8-bit identity comparator module sn74521 (p7, p6, p5, p4, p3, p2, p1, p0, q7, q6, q5, q4, q3, q2, q1, q0, g, p_q); input p7, p6, p5, p4, p3, p2, p1, p0; input q7, q6, q5, q4, q3, q2, q1, q0; input g; output p_q; assign #11 // 'F p_q = !(!g && {p7, p6, p5, p4, p3, p2, p1, p0} == {q7, q6, q5, q4, q3, q2, q1, q0}); endmodule /* * 74181 is straight from Fairchild's 74F181 data sheet. */ module sn74181 (s3, s2, s1, s0, m, a3, a2, a1, a0, b3, b2, b1, b0, f3, f2, f1, f0, ci, co, g, p, abeq); input m; input s3, s2, s1, s0; input a3, a2, a1, a0; input b3, b2, b1, b0; output f3, f2, f1, f0; input ci; output co, p, g, abeq; wire p0 = !(a0 | (s0 & b0) | (s1 & !b0)); wire p1 = !(a1 | (s0 & b1) | (s1 & !b1)); wire p2 = !(a2 | (s0 & b2) | (s1 & !b2)); wire p3 = !(a3 | (s0 & b3) | (s1 & !b3)); wire g0 = !((!b0 & s2 & a0) | (a0 & b0 & s3)); wire g1 = !((!b1 & s2 & a1) | (a1 & b1 & s3)); wire g2 = !((!b2 & s2 & a2) | (a2 & b2 & s3)); wire g3 = !((!b3 & s2 & a3) | (a3 & b3 & s3)); wire u0 = !(ci & !m); wire u1 = !m & p0; wire u2 = !m & ci & g0; wire u3 = !m & p1; wire u4 = !m & p0 & g1; wire u5 = !m & ci & g0 & g1; wire u6 = !m & p2; wire u7 = !m & p1 & g2; wire u8 = !m & p0 & g1 & g2; wire u9 = !m & ci & g0 & g1 & g2; wire u10 = !(g0 & g1 & g2 & g3); wire u11 = !(ci & g0 & g1 & g2 & g3); wire u12 = p0 & g1 & g2 & g3; wire u13 = p1 & g2 & g3; wire u14 = p2 & g3; wire u15 = p3; wire u16 = !(u12 | u13 | u14 | u15); // propagation delays are from the data sheet and are the max. // delays. assign #13 f0 = u0 ^ p0 ^ g0; assign #13 f1 = !(u1 | u2) ^ p1 ^ g1; assign #13 f2 = !(u3 | u4 | u5) ^ p2 ^ g2; assign #13 f3 = !(u6 | u7 | u8 | u9) ^ p3 ^ g3; assign #15 co = !u11 | !u16; assign #11 p = u10; assign #10 g = u16; assign #29 abeq = (f0 & f1 & f2 & f3) ? 1'b0 : 1'bZ; // OC endmodule module sn74182 (cn, p0, g0, p1, g1, p2, g2, p3, g3, \cn+x , \cn+y , \cn+z , g, p); input cn, g0, p0, g1, p1, g2, p2, g3, p3; output \cn+x , \cn+y , \cn+z , g, p; // From the data sheet. But Fairchild's is in error and has an NOR // gate instead of an OR gate for /G. Philips^WNXP^WNexperia got it // right, we see. assign #10 \cn+x = !((g0 & p0) | (g0 & !cn)); assign #10 \cn+y = !((g1 & p1) | (g0 & g1 & p0) | (!cn & g0 & g1)); assign #10 \cn+z = !((g2 & p2) | (g1 & g2 & p1) | (g0 & g1 & g2 & p0) | (!cn & g2 & g1 & g0)); assign #12 g = (g3 & p3) | (g2 & g3 & p2) | (g1 & g2 & g3 & p1) | (g0 & g1 & g2 & g3); assign #9 p = (p3 | p2 | p1 | p0); endmodule module sn7438x (a0, a1, a2, a3, b0, b1, b2, b3, cn, s0, s1, s2, f0, f1, f2, f3, cn4, ovr, p, g); input a0, a1, a2, a3; input b0, b1, b2, b3; input cn, s0, s1, s2; output f0, f1, f2, f3; output cn4, ovr; output p, g; wire s0_d, s1_d, s2_d; assign #5 s0_d = s0; assign #5 s1_d = s1; assign #5 s2_d = s2; wire k0 = !(!s0_d & !s1_d); wire k1 = !(!s1_d & !s2_d); wire p28 = !s0_d & !s1_d; wire p29 = !(!s0_d & s1_d); wire p30 = !(s0_d & s1_d & !s2_d); wire p31 = !s1_d & s2_d; wire q8 = !s0_d & s2_d; wire u0 = !(q8 | p31); // wire p0 = !b0 & !a0 & k1 & p29; wire p1 = !b0 & a0 & k0 & p29 & p30; wire p2 = b0 & !a0 & k1 & p30; wire p3 = !a0 & !b0 & k0 & p30 & u0; wire p4 = !b0 & a0 & k1 & p29; wire p5 = b0 & !a0 & k1 & p29; wire p6 = b0 & a0 & k0 & p30; // wire p7 = !b1 & !a1 & k1 & p29; wire p8 = !b1 & a1 & k0 & p29 & p30; wire p9 = b1 & !a1 & k1 & p30; wire p10 = !a1 & !b1 & k0 & p30 & u0; wire p11 = !b1 & a1 & k1 & p29; wire p12 = b1 & !a1 & k1 & p29; wire p13 = b1 & a1 & k0 & p30; // wire p14 = !b2 & !a2 & k1 & p29; wire p15 = !b2 & a2 & k0 & p29 & p30; wire p16 = b2 & !a2 & k1 & p30; wire p17 = !a2 & !b2 & k0 & p30 & u0; /* 0 0 */ wire p18 = !b2 & a2 & k1 & p29; /* 0 1 */ wire p19 = b2 & !a2 & k1 & p29; /* 1 0 */ wire p20 = b2 & a2 & k0 & p30; /* 1 1 */ // wire p21 = !b3 & !a3 & k1 & p29; wire p22 = !b3 & a3 & k0 & p29 & p30; wire p23 = b3 & !a3 & k1 & p30; wire p24 = !b3 & !a3 & k0 & p30 & u0; wire p25 = !b3 & a3 & k1 & p29; wire p26 = b3 & !a3 & k1 & p29; wire p27 = b3 & a3 & k0 & p30; // wire q0 = !(p0 | p1 | p2); wire q1 = !(p3 | p4 | p5 | p6); wire q2 = !(p7 | p8 | p9); wire q3 = !(p10 | p11 | p12 | p13); wire q4 = !(p14 | p15 | p16); wire q5 = !(p17 | p18 | p19 | p20); wire q6 = !(p21 | p22 | p23); wire q7 = !(p24 | p25 | p26 | p27); // // wire u1 = !(p28 | s2_d); // // wire w0 = !(q0 & u1); /* Motorolla */ wire w0 = !(cn & u1); /* Fairchild */ // wire w1 = cn & q0 & u1; wire w2 = q0 & q1 & u1; // wire w3 = cn & q0 & q2 & u1; wire w4 = q0 & q2 & q1 & u1; wire w5 = q2 & q3 & u1; // wire w6 = cn & q0 & q2 & q4 & u1; wire w7 = q0 & q2 & q4 & q1 & u1; wire w8 = q2 & q4 & q3 & u1; wire w9 = q4 & q5 & u1; // wire w10 = !(q0 & q2 & q4 & q6); wire w11 = q0 & q2 & q4 & q6 & q1; wire w12 = q2 & q4 & q6 & q3; wire w13 = q4 & q6 & q5; wire w14 = q6 & q7; wire w15 = !(cn & q0 & q2 & q4 & q6); // wire v0 = !(w1 | w2); wire v1 = !(w3 | w4 | w5); wire v2 = !(w6 | w7 | w8 | w9); wire v3 = !(w11 | w12 | w13 | w14); wire v4 = v3 & w15; wire v5 = !(v3 & w15); // // wire v4 = v3 & w15; // wire v5 = !(v3 & w15); // wire x0 = w0 ^ q1; wire x1 = v0 ^ q3; wire x2 = v1 ^ q5; wire x3 = v2 ^ q7; wire x4 = v2 ^ v4; assign #16 f0 = x0; assign #16 f1 = x1; assign #16 f2 = x2; assign #16 f3 = x3; assign #12 cn4 = v5; assign #12 ovr = x4; assign #10 p = w10; // ??? assign #10 g = v3; // ??? endmodule module sn74382 (a0, a1, a2, a3, b0, b1, b2, b3, cn, s0, s1, s2, f0, f1, f2, f3, cn4, ovr); input a0, a1, a2, a3; input b0, b1, b2, b3; input cn, s0, s1, s2; output f0, f1, f2, f3; output cn4, ovr; sn7438x U1 (.a0(a0), .a1(a1), .a2(a2), .a3(a3), .b0(b0), .b1(b1), .b2(b2), .b3(b3), .cn(cn), .s0(s0), .s1(s1), .s2(s2), .f0(f0), .f1(f1), .f2(f2), .f3(f3), .cn4(cn4), .ovr(ovr)); endmodule module sn74381 (a0, a1, a2, a3, b0, b1, b2, b3, cn, s0, s1, s2, f0, f1, f2, f3, p, g); input a0, a1, a2, a3; input b0, b1, b2, b3; input cn, s0, s1, s2; output f0, f1, f2, f3; output p, g; sn7438x U1 (.a0(a0), .a1(a1), .a2(a2), .a3(a3), .b0(b0), .b1(b1), .b2(b2), .b3(b3), .cn(cn), .s0(s0), .s1(s1), .s2(s2), .f0(f0), .f1(f1), .f2(f2), .f3(f3), .p(p), .g(g)); endmodule module oldsn74882 (p0, p1, p2, p3, p4, p5, p6, p7, g0, g1, g2, g3, g4, g5, g6, g7, cn, cn4, cn8, cn16, cn24, cn32); input p0, p1, p2, p3, p4, p5, p6, p7; input g0, g1, g2, g3, g4, g5, g6, g7; input cn; output cn4, cn8, cn16, cn24, cn32; assign #12 cn32 = !(g7 & p7 | g7 & g6 & p6 | g7 & g6 & g5 & p5 | g7 & g6 & g5 & g4 & p4 | g7 & g6 & g5 & g4 & g3 & p3 | g7 & g6 & g5 & g4 & g3 & g2 & p2 | g7 & g6 & g5 & g4 & g3 & g2 & g1 & p1 | g7 & g6 & g5 & g4 & g3 & g2 & g1 & g0 & p0 | g7 & g6 & g5 & g4 & g3 & g2 & g1 & g0 & !cn); assign #12 cn24 = !(g5 & p5 | g5 & g4 & p4 | g5 & g4 & g3 & p3 | g5 & g4 & g3 & g2 & p2 | g5 & g4 & g3 & g2 & g1 & p1 | g5 & g4 & g3 & g2 & g1 & g0 & p0 | g5 & g4 & g3 & g2 & g1 & g0 & !cn); assign #12 cn16 = !(g3 & p3 | g3 & g2 & p2 | g3 & g2 & g1 & p2 | g3 & g2 & g1 & g0 & p0 | g3 & g2 & g1 & g0 & !cn); assign #12 cn8 = !(g1 & p1 | g1 & g0 & p0 | g1 & g0 & !cn); endmodule module sn74882 (p0, p1, p2, p3, p4, p5, p6, p7, g0, g1, g2, g3, g4, g5, g6, g7, cn, cn4, cn8, cn16, cn24, cn32); input p0, p1, p2, p3, p4, p5, p6, p7; input g0, g1, g2, g3, g4, g5, g6, g7; input cn; output cn4, cn8, cn16, cn24, cn32; wire cn_d; assign #7 cn_d = cn; assign #12 cn32 = !(g7 & p7 | g7 & g6 & p6 | g7 & g6 & g5 & p5 | g7 & g6 & g5 & g4 & p4 | g7 & g6 & g5 & g4 & g3 & p3 | g7 & g6 & g5 & g4 & g3 & g2 & p2 | g7 & g6 & g5 & g4 & g3 & g2 & g1 & p1 | g7 & g6 & g5 & g4 & g3 & g2 & g1 & g0 & p0 | g7 & g6 & g5 & g4 & g3 & g2 & g1 & g0 & !cn_d); assign #10 cn24 = !(g5 & p5 | g5 & g4 & p4 | g5 & g4 & g3 & p3 | g5 & g4 & g3 & g2 & p2 | g5 & g4 & g3 & g2 & g1 & p1 | g5 & g4 & g3 & g2 & g1 & g0 & p0 | g5 & g4 & g3 & g2 & g1 & g0 & !cn_d); assign #7 cn16 = !(g3 & p3 | g3 & g2 & p2 | g3 & g2 & g1 & p2 | g3 & g2 & g1 & g0 & p0 | g3 & g2 & g1 & g0 & !cn_d); assign #7 cn8 = !(g1 & p1 | g1 & g0 & p0 | g1 & g0 & !cn_d); endmodule